syntax - VHDL code for register, to use in a binary multiplication circuit -

syntax - VHDL code for register, to use in a binary multiplication circuit -

i wrote piece vhdl code register (to create shift register circuit) in binary multiplication circuit. 1 time analyzed in quartus ii several syntax errors displayed.

this code:

entity memory port (can_load, can_shift, can_ad, sb_input, ab_input, userinput : in bit; out_bit, z : out bit); end memory; architecture logic of memory signal state: bit := '0'; begin if (can_load = '1') state <= userinput; else if (can_ad = '1') z <= state; --z output goes 4 bit adder state <= ab_input; end if; if (can_shift = '1') out_bit <= state; state <= sb_input; end if; end if; end logic;

this error messages:

info: *******************************************************************

info: running quartus ii 64-bit analysis & synthesis info: version 14.0.0 build 200 06/17/2014 sj web edition info: processing started: sun oct 19 16:28:22 2014 info: version 14.0.0 build 200 06/17/2014 sj web edition info: processing started: sun oct 19 16:28:22 2014

info: command: quartus_map --read_settings_files=on --write_settings_files=off memory -c memory

warning (20028): parallel compilation not licensed , has been disabled

error (10500): vhdl syntax error @ memory.vhd(9) near text "if"; expecting "end", or "(", or identifier ("if" reserved keyword), or concurrent statement

error (10500): vhdl syntax error @ memory.vhd(9) near text "then"; expecting "<="

error (10500): vhdl syntax error @ memory.vhd(11) near text "else"; expecting "end", or "(", or identifier ("else" reserved keyword), or concurrent statement

error (10500): vhdl syntax error @ memory.vhd(12) near text "then"; expecting "<="

error (10500): vhdl syntax error @ memory.vhd(15) near text "if"; expecting ";", or identifier ("if" reserved keyword), or "architecture"

error (10500): vhdl syntax error @ memory.vhd(16) near text "then"; expecting "<="

error (10500): vhdl syntax error @ memory.vhd(19) near text "if"; expecting ";", or identifier ("if" reserved keyword), or "architecture"

info (12021): found 0 design units, including 0 entities, in source file memory.vhd

i have checked several books right syntax, , code examples , yet cannot find where's mistake.

i tried take away parentheses in sections this:

if (can_load = '1')

having this:

if can_load = '1'

but ended of same syntax errors.

i'd appreciate help solve issue. give thanks you.

i used different tool demonstrate errors:

ghdl -a memory.vhdl memory.vhdl:9:9: generate statement must have label memory.vhdl:9:29: 'generate' expected instead of 'then' ghdl: compilation error

note analyzer complaining generate statement. because if statement sequential statement found in process or other concurrent statement or in subprogram.

a generate statement conditional scheme (hence if) concurrent process statement , requires label.

putting if statement in process:

entity memory port (can_load, can_shift, can_ad, sb_input, ab_input, userinput : in bit; out_bit, z : out bit); end memory; architecture logic of memory signal state: bit := '0'; begin some_process: process (userinput, ab_input, state, sb_input) begin if can_load = '1' state <= userinput; else if can_ad = '1' z <= state; --z output goes 4 bit adder state <= ab_input; end if; if can_shift = '1' out_bit <= state; state <= sb_input; end if; end if; end process; end logic;

analyzes.

note added userinput, ab_input, state, , sb_input process sensitivity list (everything showed on right hand side of assignment).

the presence of state brings point. new value of state not available in current simulation cycle. in illustration value of out_bit value of state found before process executed.

and in cases parentheses in if statement status superfluous. parentheses required cases when left right evaluation order isn't sufficient determine right meaning (e.g. mixing and , or operators), operators functions, , functions expressions.

syntax vhdl cpu-registers binary-logic