I am a newbie in verilog. I am searching online and most of them suggest that using loop in Verlog coding. Do not So is there a better option to change the loop? The problem I am facing now is that I have to loop for 1 or 2 in the case statement. And I was thinking about better options but did not come with any
example of my code:
always @ (*) case (help) 4 ' D1 It would be great if any of you put some light on it. For start (i = A, i & lt; = 20; i = i + b) start temporarily [i-1] = 1; For end 4'd2: (i = A, i & lt; = 20; i = i + b) floating start [i-1] = 1; B = B + 1; End 4'd3: To start (i = A, i & lt; = 20; i = i + b) Temporary start [i-1] = 1; B = B + 1; (I = a; i> = 1; i = i-b) start ending the temporary [i-1] = 1; B = B + 1; Final end default: temp = 0; For verilog-loops are fine, but they need to be able to stabilize, so if
If you plan for synthesizing, static anol means that the loop is not dependent on any external variable. For example, for (i = 0; i & lt; 10; i = i + 1) is constant. For (i = A, i & lt; = 20; i = i + b) is not static because it depends on a variable a and B .
You can create a static to run the variable as a condition inside the loop (i = a, i & lt; = 20; i = i + b) for < / Code> becomes:
tmp_var = A; Start for (i = 0; i & lt; = 20; i = i + 1) if (i == tmp_var) // start ... your argument here ... tmp_var = tmp_var + b; End of End
Those issues which need to be addressed beyond the scope of the question:
The way you b and temporary are slightly related.
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b appears to be an input, but if you are also increasing it is illegal to manipulate this input for synthesis if it is an input, Create a local variable as the default value in the form of B and you can always change it later in the block. If this is not input, then it is making a logging argument; Which is not good and I will cover the next temp with it
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adding temporary logic is flexible argument is difficult Because time is important; When the litter is transparent or closed, and hold while recognizing the time requirements to learn. The more complex logic argument is difficult, it is predictable. Inclined side-by-side assignments in RTL on one side of the estimated blocks (i.e. always @ * ). To solve this, make sure that each bit is assigned to each pass of the combination blocks. One of the safest safeguards is to assign a default value to your logic before moving it. Example:
always @ (*) start temporary = 0; // default for a constant temp_B = b; // one input value // default ... your logic ... end