logical operators - VHDL unexpected behaviour of XNOR for std_logic_vector -

In my structural VHDL code I have a series of 25 64bit studs_lallis_witers. It should always be the same and I want to check if there is a flaw that flips a bit, my code looks like this:

  outx < = Mt1_op XNOR mr2_op Xnor mt3_op XNOR .... XNR MT 25_p;  

It does not give me any errors and is properly synthesized, but when I simulate it in ISIM, the XNRR operation does not work. I hope all 1s or sometimes 0 if there is a mistake, but the final output signal, outx, is just the same value as all the input signals. I will not bother telling the whole 64 bit vector, but as an unsigned difference it resolves 7776. All the Ventures are 7776 - and when I add them all together, I get an answer of 7776.

I suspect that the problem can be applied once by XNOR operations, i.e.

  outx < = (Mt1_op XNOR mt2_op XNOR (mt3_op XNOR (mt4_op XNOR (. ....))))))))))));  

will not give the desired behavior

Do anyone have the idea that how can I get the behavior I want? That is, if all 25 vectors are equal, then give me all 1s or have differences, give me 0.

Thanks

Tom

This is working fine Is:

  '0' XNOR '0' Xnor ... XNOR '0' = '0 - 25 XNOR' 0 '' 1 'XnOR' 1 'XNOR ... XNOR' 1 Expression logic vector will return for '=' 1 '- 25 for XNOR' 1's  

if the same vector is given 25 times for XNOR is.

To check that all the vectors are the same you can:

  or_all & lt; = Mt1_op or mt2_op or ... or mt25_op; And _ all & lt; = Mt1_op and mt2_op and ... and mt25_op; Similar & lt; = Or_all = and_all;  

as the type of boolean and std_logic

  identical_st_logic for the resulting type & lt; = '1' when (and_all) = or_now) Other '0';