verilog - how to generate delay on xilinx spartan 6 board? -

verilog - how to generate delay on xilinx spartan 6 board? -

i learning verilog hdl. , now, trying run programme on digilent atlys spartan 6 xc6slx45. implementing counter on board.

module counter_s2( output reg [7:0] count); initial begin count=0; repeat(127) begin #10000000 count=count+1; end end endmodule

when run code on board, final input of 1111111. there no delay coming on board. want produce delay of, lets 1 second, see output. thanks!

p.s: new verilog.

what have created fine testbench component , work in simulation, parts of not synthesisable.

in particular initial can used on fpgas set initial values, can not alter on time in block, updated in separate block. nb: time when 2 blocks can set same reg.

#delay values ignored synthesis. arbitrary asynchronous timing command can not implemented reliably , not part of synthesis tools.

to develop verilog counters clock used, meant counter value held in flip-flop. count observable need clock slow enough.

the next counter overflow , maintain counting continuously

module counter_s2( input clk, output reg [7:0] count ); initial begin count= 'b0; end @(posedge clk) begin count <= count + 1 ; end endmodule

if asic should using resets instead of relying on initial.

module counter_s2( input clk, input rst_n, //active low reset output reg [7:0] count ); @(posedge clk or negedge rst_n) begin if (~rst_n) begin count <= 'b0; end else begin count <= count + 1 ; end end endmodule

delay verilog